A level shifter is used for converting a narrow-range input signal into a wide-range output signal.
FIG. 1 is a schematic circuit diagram illustrating a conventional level shifter. In the conventional level shifter 100, an input signal Sin is changed between a first high logic level and a low logic level, and an output signal Sout is changed between a second high logic level and the low logic level. For example, the low logic level is equal to a first voltage Vss, the first high logic level is equal to a second voltage Vdd, and the second high logic level is equal to a third voltage Vpp.
As shown in FIG. 1, the conventional level shifter 100 comprises a first inverter 110, an output buffering unit 120, and plural transistors Mp1, Mp2, Mn1 and Mn2. The output buffering unit 120 comprises a second inverter 122 and a third inverter 123.
The first inverter 110 is operated in a voltage range between the second voltage Vdd and the first voltage Vss for converting the input signal Sin into an inverted input signal Sinb. Moreover, the second inverter 122 and the third inverter 123 are operated in a voltage range between the third voltage Vpp and the first voltage Vss. Moreover, the third voltage Vpp is larger than the second voltage Vdd, and the second voltage Vdd is larger than the first voltage Vss.
The source terminal of the transistor Mp1 receives the third voltage Vpp. The drain terminal of the transistor Mp1 is connected with a node a1. The gate terminal of the transistor Mp1 is connected with a node a2. The source terminal of the transistor Mp2 receives the third voltage Vpp. The drain terminal of the transistor Mp2 is connected with the node a2. The gate terminal of the transistor Mp2 is connected with the node a1. The source terminal of the transistor Mn1 receives the first voltage Vss. The drain terminal of the transistor Mn1 is connected with the node a1. The gate terminal of the transistor Mn1 receives the input signal Sin. The source terminal of the transistor Mn2 receives the first voltage Vss. The drain terminal of the transistor Mn2 is connected with the node a2. The gate terminal of the transistor Mn2 receives the inverted input signal Sinb.
The second inverter 122 and the third inverter 123 of the output buffering unit 120 are connected with each other in series. The input terminal of the second inverter 122 is connected with the node a2. The output terminal of the third inverter 123 generates the output signal Sout.
In case that the input signal Sin has the low logic level (i.e. the first voltage Vss), the inverted input signal Sinb has the first high logic level (i.e. the second voltage Vdd). Under this circumstance, the transistor Mn2 is turned on, the transistor Mn1 is turned off, the transistor Mp1 is turned on, and the transistor Mp2 is turned off. The voltage at the node a1 is equal to the third voltage Vpp, and the voltage at the node a2 is equal to the first voltage Vss. Consequently, the output signal Sout from the output buffering unit 120 has the low logic level (i.e. the first voltage Vss).
In case that the input signal Sin has the first high logic level (i.e. the second voltage Vdd), the inverted input signal Sinb has the low logic level (i.e. the first voltage Vss). Under this circumstance, the transistor Mn1 is turned on, the transistor Mn2 is turned off, the transistor Mp2 is turned on, and the transistor Mp1 is turned off. The voltage at the node a1 is equal to the first voltage Vss, and the voltage at the node a2 is equal to the third voltage Vpp. Consequently, the output signal Sout from the output buffering unit 120 has the second high logic level (i.e. the third voltage Vpp).
However, the conventional level shifter 100 may suffer from N-P MOS fighting which results from the plural transistors Mp1, Mp2, Mn1 and Mn2 when the logic state of the input signal is changed, the gate delay of the conventional level shifter 100 is long. That is, after the input signal Sin is switched from the low logic level to the first high logic level, a longer time period is required to switch the output signal Sout from the low logic level to the second high logic level. Similarly, after the input signal Sin is switched from the first high logic level to the low logic level, a longer time period is required to switch the output signal Sout from the second high logic level to the low logic level. Thus, a level shifter with shorter gate delay is needed.